1. Field of the Invention
This invention relates to a structure of a semiconductor device having a plurality of semiconductor elements; more particularly, the present invention relates to the fabrication of high power semiconductor elements and a control semiconductor element on one semiconductor substrate.
2. Description of the Prior Art
Regarding a conventional semiconductor device of the type referred to, the following description will be made. FIG. 1 is a sectional view of a conventional device and shows the case where one high power transistor and one control transistor have been formed on one semiconductor substrate.
In FIG. 1, element (1) is an N type low resistance semiconductor substrate; element (2) is a first N type high resistance layer; element (3) is a P type buried layer; element (4) is an N type buried layer; element (5) is a second N type high resistance layer; element (6) is a P type wall-like layer; element (7) is an N type wall-like layer; element (8) is a P type base layer of a high power transistor; element (9) is an N type emitter layer of the transistor; element (10) is a P type base layer of a control transistor; element (11) is an N type emitter layer of the control transistor, and element (12) is a boundary between the first N type high resistance layer (2) and the second N type high resistance layer (5).
Regarding a process of manufacturing this conventional device, the following description will be made. First the N type first high resistance layer (2) is formed on the N type low resistance substrate (1) according to the epitaxial growth method. The P type buried layer (3) and the N type buried layer (4) are successively formed through diffusions after which the second N type high resistance layer (5) which is identical in its resistivity to that of the first N type high resistance layer (2) is epitaxially grown on the entire area of the upper surface thereof. Then, the P type wall-like layer (6) is formed through a diffusion to isolate the N type high resistance layers. Then, the N type wall-like layer (7) is diffused to contrive a low resistance connection to the N type buried layer (4). Thereafter, the P type base layer (8) and the N type emitter layer (9) of the high power transistor and the P type base layer (10) and the N type emitter layer (11) of the control transistor are successively formed through diffusions. The N type low resistance substrate (1) forms an ohmic region for a collector of the high power transistor and the N type wall-like layer (7) forms an ohmic region for a collector of the control transistor.
In the case of such a structure of the conventional device, the epitaxial growth is effected twice for the first N type high resistance layer (2) and the second N type high resistance layer (5). Thus, crystal defects within the second N type high resistance layer (5) have been significantly increased so as to reduce the manufacturing yields of such a device and to raise the cost of the devices. Also, since the crystal defects occur, the deterioration of the characteristics and, more particularly, of the voltage breakdown characteristics and the damage have not been avoided with respect to external surge voltages. Furthermore, there have been the disadvantages that, as the epitaxial growth is effected twice, an increase in lead time due to an increase in the process steps and also a reduction in yield due to the increase in process steps occur at the same time and so on.